Unlike a CMOS image sensor chip, Vision 
Systems on Chip (VSoC) are not only conceived for capturing images, they are also used for processing images in real time according to an algorithm that is programmed by the user. This prompts decisions based on the outcome of the image processing.
Why choose VSoC technology?
Today the cost of integrating a processing capability into a digital camera is small, however the main standard solution (consisting of digital camera + frame-grabber + PC) is still expensive due to the cost of image communication, especially in high speed applications.
In VSoC, the image capture and processing are placed in the same System on Chip (SoC), so the need for bandwidth in image communication is drastically reduced as only selected pieces of information (features, not full images) are downloaded or in some cases only decisions are prompted. As image sensing and processing co- exists in VSoC, it is very easy to imagine networks of VSoC cooperating to solve complex image processing tasks.
Their inherent scalability makes it possible to join as many VSoC as needed, working as elements of a larger processor, to practically solve many applications.
What is an Teledyne AnaFocus VSoC?
It could be considered that the obvious way of building a VSoC is by putting together a CMOS image sensor, a microprocessor, and some memory. Even when that is done, only a very small amount of real world applications can be solved with such an architecture due to the parallel nature of image processing.
Solving complex image processing tasks in real time requires enormous amounts of power processing and memory. Both of these factors are “natural enemies” of SoC solutions.
During the past 20 years, the founders of Teledyne AnaFocus have conceived and developed a patent protected architecture for performing complex and efficient image processing in an SoC. The key concept of such an architecture is parallel and multi layer image processing.
Conceptually speaking, the foundation of this processing architecture is simple, divide image processing into many elementary processing blocks and make them work together. This way, you will save a large amount of processing power and image memory when compared to the standard “sensor + CPU” paradigm.
Teledyne AnaFocus’ VSoC architecture also exploits the concept of analog image processing.
After many years of research and numerous chips we discovered that certain image processing operations can be implemented in analog with good accuracy and outstanding power and area efficiency. Such operators are applied directly to the analog images from the pixel array, before digitalization. Such analog processing blocks can be physically placed right in the pixel array or in the shape of column wise analog processors that operate as the image is read row by row.
This concept (arranged in the proper architecture), results in ultra efficient VSoC architectures which rival in performance more sophisticated and expensive multi chip smart cameras, while still keeping the size and price advantage of single chip.
How is a VSoC designed?
Creating a VSoC is a complex task involving an image sensor and SoC design, software hardware co-design and real time image processing. Teledyne AnaFocus owns a proprietary and silicon proven methodology for mapping a vision application (this is an application involving image capture, image processing, and data communication) into a high performance and cost effective SoC.
Such a methodology has been successfully applied to the development of innovative and powerful VSoC for top tier companies who today enjoy a market advantage provided by the availability of such exclusive and differentiated devices.